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Responsibilities:

• ASIC design engineer, work with algorithm team to define system architecture, implement RTL design and verification.
• Take part in all stages in digital design flow, including system analysis, timing analysis, formal verification, DFT design, FPGA and chip test.

Requirements:

• MS or Ph.D degree in EE, CS, communications, micro-electronics
• Experience in Verilog HDL, solid understanding of digital circuit, knowledge on ASIC design flow and EDA tools for simulation and synthesis.
• Fluent in C/C++, Perl/Shell scripts.
• CET-4, English document reading ability is required.
• Should be able to write technical documents following standard writing guideline.
• Good communication skill, team player with responsibility and passion
• Following experience is preferred:
  • Experience in DSP, digital communication, audio processing, peripheral(USB, MIPI, etc)
  • Experience in low power design