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October 29, 2021
As the world’s first open-source processor architecture, RISC-V could eliminate costly licenses, kickstart new innovation, and improve global partnerships across the developer community.
RISC-V (pronounced “risk-five”) is what’s known as an instruction set architecture (ISA). Originally designed to support computer architecture research and education, it is now an open specification and platform designed to support extensive customization and specialization.
RISC-V is significant because it allows smaller device manufacturers to build hardware without paying royalties. It also enables developers and researchers to design and experiment with a proven and freely available ISA. This article will explain the evolution of RISC-V with a look at its ecosystem, comparison with ARM, and its adoption in today’s Internet of Things (IoT).
RISC dates back to the early 1980s. Simple, effective computers have always been of academic interest, which led to the creation of the original RISC instruction set DLX for use in the first edition of the 1990 Hennessy & Patterson textbook Computer Architecture: A Quantitative Approach.
The RISC-V project started in 2010 at the University of California, Berkeley, along with volunteer contributors not affiliated with the university. It is the eponymous fifth generation of RISC-based research projects, and unlike the original ISA that was intended primarily for educational purposes, RISC-V is suitable for both commercial and academic deployment. A formal RISC-V Foundation — recently renamed as RISC-V International — was incorporated to own, maintain, and publish the RISC-V definition.
Today, RISC-V members have grown from 29 original members to over 1000 members, including Telink, as well as founding companies like Google, Andes Technology, ICT, and Western Digital. Members represent more than 50 countries across multiple industries.
The RISC-V authors originally sourced the ISA documents and CPU designs under BSD licenses. This license allowed RISC-V chip designs to be either open (free) or closed (proprietary). The ISA specification itself was published in 2011 as open-source and later placed under a Creative Commons license that allows contributors to build upon, share, and use it freely.
On a technical level, RISC-V actually does not incorporate any new features. Rather, it follows established RISC principles and uses a load-store architecture. As such, it does not violate any known patents, and like other ISAs, the specification defines different levels of instruction sets, which include 32 and 64-bit variants and extensions to support floating point instructions. This allows for the development of versions suited to a range of applications, from small embedded microcontrollers to desktop personal computers and even supercomputers with vector processors.
The hardware and software in the RISC-V ecosystem is extensive and includes:
This ecosystem is necessary for RISC-V to be successful. The components spread across all layers from low-level firmware and boot loaders to a fully functional operating system kernel, applications, design, and verification tools.
Today, over 100 RISC-V cores and over 40 RISC-V SoCs and SoC platforms are available, with these numbers constantly growing.
Prior to the introduction of RISC-V, Advanced RISC Machine (ARM) had been the dominant CPU architecture for microcontrollers, microprocessors, and mobile systems. ARM processors are extensively used in consumer electronic devices like smartphones, tablets, and other mobile devices, including wearables. The ARM architecture has fewer sets of predefined instructions, which leverages the efficiency of simplicity with the goal of rendering all of the processor’s functionality on a single chip. This simple nature helps chips efficiently perform millions of instructions per second (MIPS).
While both ARM and RISC-V are somewhat similar in function (with both being load-store and RISC), RISC-V is open-source whereas ARM is proprietary. As RISC-V is open-source, anyone with an Internet connection can look up the standard and implement their own design. Meanwhile, designers looking to integrate an ARM CPU into their design are required to pay royalties to ARM holdings. Because ARM is proprietary, it also risks being export-blocked by governments — for example, the U.S. attempted to block the sale of ARM IP to China. More recently, the U.S. company Nvidia sought to acquire ARM, though the deal is currently stalled.
The use of RISC-V is increasing, with many major companies looking at it as an alternative to ARM. As technology continues to shape RISC-V’s evolution, it’ll become a close competition between a paid-for processor architecture or a free architecture with no limitations. RISC-V is a game-changer in the ISA space, and as a Strategic Member of RISC-V International, Telink is committed to bringing reliable, highly-performant, and innovative solutions for the IoT to market. That commitment means embracing all that RISC-V has to offer, as demonstrated by last year’s launch of the new TLSR9 series, a high-performing, RISC-V-based system-on-a-chip (SoC) designed for wireless audio, wearable devices, and a variety of cutting-edge IoT applications.
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