In the role of Senior CAD / Methodology Engineer focused on DFT implementation you will be responsible for developing methods for executing DFT, and work to automate the flow through scripting and programming. You will work with digital design and backend teams to roll out these flows for complex SoC chips, and work with ATE team and QA team to improve the yield.
- 5+ years of experience with methodology and flow implementation for large ASIC chips.
- 3+ years of experience with industry standard DFT tools from Synopsys, Mentor, and Cadence.
- Expert at scripting using Perl, TCL or other scripting/programming languages.
- Experience with AC/DC scan insertion, MBIST and JTAG.
- Ability to work independently.
- Good communications skills.
- Education: BSEE required.
- Knowledge of Cadence DFT flow.
- Expertise of low power flow is a plus.
- Expertise in Formality/Conformal is a plus.
- Expertise in RTL/post netlist simulation is a plus.
- MSEE preferred.